module datapath(iClk, Control, Opcode)

input iClk;
input [14:0] Control;
output [5:0] Opcode;

wire RegDst,Jump,Branch,MemRead,MemtoReg,MemWrite,ALUsrc,RegWrite,zero;
wire [5:0]ALUop;

assign RegDst=Control[14];
assign Jump=Control[13];
assign Branch=Control[12];
assign MemRead=Control[11];
assign MemtoReg=Control[10];
assign ALUop[5:0]=Control[9:4];
assign MemtoReg=Control[3];
assign MemWrite=Control[2];
assign ALUsrc=Control[1];
assign RegWrite=Control[0];

InstuctionMemory IM00(iClk, 0, ReadAddress, 32'b0, Instruction);

RegisterFile RF00(iClk, RegWrite,  WritedataReg, Writeregister, Readregister1, Readregister2, ReaddataReg1, ReaddataReg2);

DataMemory DM00(iClk, MemWrite, Address, WritedataData, ReaddataData,  MemRead);

Mux10to5 Mux00(Instuction[20:16],Instuction[15:11],MuxtoWriteregister,RegDst);
Mux64to32 Mux01(ReaddataReg2,SignExtoutput,MuxtoALU,ALUsrc);
Mux64to32 Mux02(ALUresult,ReaddataData,MuxtoWritedataReg,MemtoReg);

adder_32bit Adder00(PCout,00000000000000000000000000000100,PCplus4);
Shifterzerofront Shifterfront00(Instruction[25:0],ShiftedInstruction);  
adder_32bit Adder01(PCplus4,shiftedsignextend,Adderresult);   
Mux64to32 Mux03(PCplus4,Adderresult,Mux3result,Mux3bit);
and and00(Mux3bit,Branch,zero);
Mux64to32 Mux04(Mux3result,Jumpaddress,PCin,Jump);

SignExtend SE00(Instruction[15:0],signextend);   
Shifternonzero Shifter00(signextend,shiftedsignextend);    

ALU alu00(ReaddataReg1,MuxtoALU,ALUcontrol,ALUresult,zero);    
ALUcontrol alucontrol00(Instruction[5:0],ALUop,ALUcontrol);    

endmodule
